Dear All,
I am making an SMPS PCB which has voltage levels from 5V-12V and also 400V.
Is there any method to incorporate in Design Rules so that the spacing constraint (part to part) and different traces are automatically checked or shown later in DRC error
I am making an SMPS PCB which has voltage levels from 5V-12V and also 400V.
Is there any method to incorporate in Design Rules so that the spacing constraint (part to part) and different traces are automatically checked or shown later in DRC error
Statistics: Posted by sachindevassy — Yesterday, 22:34 — Replies 0 — Views 17
